The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to integration of electrostatic discharge protection into vertical fin technology.
In an integrated circuit, each metal oxide semiconductor field effect transistor (MOSFET) has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. Complementary metal oxide semiconductor (CMOS) is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. The channel region connects the source and the drain, and electrical current flows through the channel region from the source to the drain. The electrical current flow is induced in the channel region by a voltage applied at the gate electrode.
A grounded-gate NMOS (ggNMOS) device is an electrostatic discharge (ESD) device used within CMOS integrated circuits. ESD devices protect the inputs and outputs of an integrated circuit (e.g., an input output (I/O) device), which can be accessed off-chip, such as by wire-bonding to the pins of a package or directly to a printed circuit board, and are therefore subject to electrostatic discharge when touched. An ESD event can deliver a large amount of energy to the chip, potentially destroying input/output circuitry. A ggNMOS device provides a safe path for current to flow, ultimately to the substrate, instead of through more sensitive circuitry.